1. Field of the Invention
This invention relates to a process for making an electronic device, more particularly to a process for making an electronic device that has a multilevel interconnection structure.
2. Description of the Related Art
With the rapid technological advancement in electronic devices, miniaturization thereof has been a primary concern of manufacturers. It is desirable that the electronic devices are highly integrated and have a multilevel interconnection structure which normally includes a substrate and levels of isolated conductive paths and interconnections on the substrate.
Conventionally, the levels of the conductive paths and interconnections of the multilevel interconnection structure are formed by a process that involves selective photo-etching of a thin metal film formed by sputtering or vacuum deposition of metal over the substrate. However, the process as such is disadvantageous in that a certain degree of unevenness results for each level of the conductive paths and interconnections, and that the unevenness is aggravated as an increasing number of levels of the conductive paths and interconnections is formed.
U.S. Pat. No. 3,988,214 disclosed a method of manufacturing a semiconductor device. As illustrated in FIGS. 1A to 1E, the method involves the steps of depositing a conductive metal film 401 on a semiconductor substrate 101 (see FIG. 1A), selectively and porously anodizing the conductive metal film 401 to form a metal oxide porous layer 404 and to define conductive channels 201 which are isolated by the porous layer 404 in the metal film 401 (see FIG. 1B), barrier anodizing each conductive channel 201 to form a metal oxide non-porous layer 502 that encloses the conductive channel 201 (see FIG. 1C), and forming an opening 503 in the non-porous layer 502 so as to expose a portion of the conductive channel 201 from the non-porous layer 502 to permit external connection (see FIG. 1D). In an alternative way, the conductive channel 201 in FIG. 1B is selectively barrier anodized such that the non-porous layer 502 only covers a portion of an upper surface of the conductive channel 201. The remaining portion of the upper surface of the conductive channel 201 is used to establish an external connection (see FIG. 1E).
Although the method proposed in the patent can alleviate the aforesaid unevenness problem, there is still a certain degree of unevenness between the porous layer 404 and the non-porous layer 502 due to a greater bulk volume change for the porous layer 404 than that for the non-porous layer 502 during the anodization of the metal film 401 or the conductive channel 201, and a need to further improve the evenness of each wiring level of the semiconductor device.
U.S. Pat. No. 5,580,825 disclosed a process for forming a multilevel electronic interconnect structure. As illustrated in FIGS. 2A to 2F, the process involves the steps of depositing a main aluminum layer 7 on a substrate 1 (see FIG. 2A) selectively barrier anodizing the main aluminum layer 7 to form a surface barrier oxide layer 72 (similar to the aforesaid non-porous layer 502 disclosed in U.S. Pat. No. 3,988,214) on the main aluminum layer 7 (see FIG. 2B) and to define first level conductive paths 2 in the main aluminum layer 7 underneath the surface barrier oxide layer 72 (see FIG. 2C), providing an upper aluminum layer 12 over the main aluminum layer 7 (see FIG. 2D), and selectively anodizing the main and the upper aluminum layers 7, 12 to form a porous layer 15 and to define contact pads 3, 5, and contact vias 6 (see FIGS. 2E and 2F) which are isolated by the porous layer 15.
The process suffers the same drawback that is associated with the aforementioned method disclosed in U.S. Pat. No. 3,988,214. Moreover, because the formation of the contact pads 3, which are to be respectively connected to the conductive paths 2, is carried out after the formation of the conductive paths 2, each of the contact pads 3 has a geometric dimension greater than that of the respective conductive path 2, thereby reducing the ability to accommodate a more complex and a higher density of the contact pads 3, 5, the conductive paths 2, and the contact vias 6 in the multilevel interconnection structure of the semiconductor device.
Therefore, the object of the present invention is to provide a process for making an electronic device that is capable of overcoming the aforementioned drawbacks.
According to the present invention, there is provided a process for making an electronic device. The process comprises the steps of: preparing a substrate having an insulative planar surface; forming a metal film over the planar surface of the substrate; selectively masking the metal film with a first mask to define an unexposed area and a first exposed area on the metal film; non-porously anodizing the metal film to form a dense non-porous oxide layer on the first exposed area of the metal film; removing the first mask from the metal film; selectively masking the metal film and the dense non-porous oxide layer with a second mask to define a second exposed area on the dense non-porous oxide layer, the second exposed area being offset from the unexposed area on the metal film; porously anodizing the metal film and the dense non-porous oxide layer to convert the dense non-porous oxide layer and the metal film at the second exposed area into a porous oxide layer; and removing the second mask from the metal film and the dense non-porous oxide layer.